1. Field of the Invention
The present invention relates to an encoding apparatus used in a digital video cassette recorder for example, which records digital image signals, wherein the encoding apparatus is used for compressing the digital image signals.
2. Description of Related Art
If digital image signals obtained by digitizing analog image signals are directly recorded on tape or other recording medium, the data amount will be so great that it usually exceeds the data capacity of the recording medium. Therefore, when recording digital image signals on tape or the like, it is necessary to compress the image signals so that the data amount will not exceed the maximum recordable limit. To achieve this, it has been known to compress image signals using a high-efficiency encoding apparatus.
One known method for compressing digital image signals, i.e., for reducing the encoding rate thereof, is a subsampling method, such as disclosed in Japanese Patent Application Laid-Open No. 63-38385, in which sampled signals are dropped at predetermined intervals. FIGS. 1 and 2 are block diagrams respectively illustrating the configurations of the transmitter side (recording side) and receiver side (reproducing side) of a high-efficiency encoding apparatus employing such a method for encoding color video signals.
Referring first to FIG. 1, we will describe the configuration of the transmitter side. A color video signal, compatible with the NTSC system, for example, is input at an input terminal 31. The input color video signal is fed to an A/D converter 32 which outputs a digital color video signal with each sample quantized into an 8-bit code at a sampling frequency of, for example, 4 fsc (fsc: color sub-carrier frequency). The digital color video signal is fed to a subsampling circuit 33 whose output signal is supplied to a blocking circuit 34. Since no band-limiting prefilters are provided at a stage preceding the subsampling circuit 33, the high-frequency components of the input color video signal will not be lost.
In the subsampling circuit 33, the digital color video signal is sampled at a sampling frequency of 2 fsc. The blocking circuit 34 divides the supplied digital color video signal into two-dimensional blocks each comprising successive signals and serving as a unit of encoding. In this prior art example, a picture of one field is divided into blocks of 32 pixels (8 pixels.times.4 lines). FIG. 3 shows one block thus obtained, in which the solid lines represent lines in an odd-numbered field and the dotted lines correspond to lines in an even-numbered field. Alternatively, four two-dimensional regions respectively belonging to four frames may be organized into a three-dimensional block, and such a three-dimensional block may be used as one block. The subsampling circuit 33 provided at the stage preceding the blocking circuit 34 decimates selected pixels within the block, as shown in FIG. 4, thereby reducing the number of pixels within one block to 16. In FIG. 4, the subsampled pixels are designated by .largecircle., and the decimated pixels designated by x.
The output signal of the blocking circuit 84 is delivered to a dynamic range (DR) detection circuit 35 as well as to a delay circuit 36. The DR detection circuit 35 detects a dynamic range DR and minimum value MIN of each block. The delay circuit 36 outputs pixel data PD to a subtracter 37 which produces pixel data PDI by removing the minimum value MIN.
The subsampled pixel data PDI, after removal of the minimum value through the subtracter 37, and the dynamic range DR are inputted to a quantizing circuit 38. The quantizing circuit 38 quantizes the pixel data PDI in accordance with the dynamic range DR and produces a code signal DT that represents one-pixel data converted into a 4-bit code.
The code signal DT outputted from the quantizing circuit 38 is transferred to a framing circuit 39. The dynamic range DR (8 bits) and the minimum value MIN (8 bits) are also input, as appended codes for each block, to the framing circuit 39. The framing circuit 39 performs error-correction coding on the code signal DT and the appended codes and appends a synchronizing signal. Transmission data is obtained at an output terminal 40 of the framing circuit 39, and the transmission data is transferred onto a transmission channel such as a digital line. In the case of a digital video cassette recorder, the output signal is transferred to a rotary head via a recording amplifier, rotary transformer, etc.
Referring to FIG. 2, we will now describe the configuration of the receiver side. The received data at an input terminal 41 is input to a frame disassembling circuit 42 which disassembles the received data into the code signal DT and the appended codes DR and MIN and performs error correction. The code signal DT and the dynamic range DR are then transferred to a decoding circuit 43.
The decoding circuit 43 carries out a decoding process which is the reverse of the process performed by the quantizing circuit 38 in the transmitter side. More specifically, the data with the 8-bit minimum value removed is decoded to a representative level, and the decoded data and the 8-bit minimum value MIN are added together by an adder 44 to reproduce the original pixel data. The output data of the adder 44 is fed to a block disassembling circuit 45. The block disassembling circuit 45 carries out a disassembling process which is the reverse of the process performed by the blocking circuit 34 in the transmitter side, rearranging the block-sequenced decoded data into the same order in which the television signal is scanned. The output signal of the block disassembling circuit 45 is transferred to an interpolation circuit 46. In the interpolation circuit 46, the approximation of the decimated pixel data is constructed by using neighboring subsampled data. The interpolation circuit 46 outputs a digital color video signal with a sampling frequency of 4 fsc to a D/A converter 47, and an analog color video signal is obtained at an output terminal 48 of the D/A converter 47. When no prefilters are provided at the transmitter side, aliasing distortion may occur, for example, at points where the brightness level abruptly changes; therefore, a circuit for eliminating this distortion may be connected to the output side of the interpolation circuit 46.
FIG. 5 is a block diagram illustrating the configuration of a conventional high-efficiency encoding apparatus described, for example, in "An Experimental Digital VCR with 40 mm Drum, Single Actuator and DCT-Based Bit-Rate Reduction", IEEE Transactions on Consumer Electronics, Vol. 34, No. 3 (August 1988). In the figure, the reference numeral 71 designates a blocking circuit for dividing an input digital image signal into a plurality of blocks. The blocking circuit 71 supplies each block of the image signal to a DCT circuit 72. The DCT circuit 72 performs a discrete cosine transform (DCT) on each block of the image signal supplied from the blocking circuit 71 and outputs transform coefficients to a weighting circuit 73. The weighting circuit 73 assigns a weighting to each transform coefficient and supplies the weighted transform coefficient to an adaptive quantizing circuit 74. The adaptive quantizing circuit 74 contains a plurality of quantization tables with different quantization levels, quantizes the weighted transform coefficient with the optimum quantization level, and outputs the quantized transform coefficient to a variable-length encoding circuit 75. The variable-length encoding circuit 75 encodes the quantized transform coefficient into a variable-length code which is then transferred to a buffer memory 76. The buffer memory 76 stores the variable-length encoded data and outputs the stored data at a fixed output rate. A buffer controller 77 controls the quantization level in the adaptive quantizing circuit 74 so that an overflow does not occur in the buffer memory 76, while selecting the transform coefficients to be encoded by the variable-length encoding circuit 75.
The operation of the above encoding apparatus will now be described in detail. The input digital image signal comprises, for example, a luminance signal and two color-difference signals. These signals are first time-divided and then divided by the blocking circuit 71 into blocks of, for example, 8 pixels.times.8 lines, which are then transferred to the DCT circuit 72. The DCT circuit 72 performs an 8-pixel discrete cosine transform, in both the horizontal and vertical directions, on each block of the image signal. First, when the image signal is denoted as x(i, j) (i, j=0, 1, . . . , 7), a horizontal 8-pixel DCT as expressed by the following equation is performed. ##EQU1##
A vertical 8-pixel DCT as expressed by the following equation is performed on the above transformed image signal f(0, j), f(m, j), and the image signal, expressed as a transform coefficient F(m, n) (m, n=0, 1, . . . , 7), is transferred to the weighting circuit 73. ##EQU2##
Each transform coefficient supplied to the weighting circuit 73 is assigned a weight. More specifically, taking advantage of the property of the human eye which is less sensitive to higher spatial frequencies, as shown in FIG. 6, smaller weightings are assigned to areas containing higher spatial frequency components and larger weightings to areas containing lower spatial frequency components. Here, the weighting factor W (m, n) can be expressed by the following equation. ##EQU3##
The output of the weighting circuit 73 is quantized by the adaptive quantizing circuit 74. Based on the transform coefficient for each block and the quantization parameter supplied from the buffer controller 77, the optimum quantization level is selected for the adaptive quantizing circuit 74, and the weighted transform coefficient is quantized with the thus selected optimum quantization level.
More specifically, a low bit quantization level is selected for image data corresponding to the rising edge of a high contrast, while for imagine data corresponding to details with small amplitudes, a high bit quantization level is selected.
The quantized transform coefficient is encoded by the variable-length encoding circuit 75 into a variable-length code which is then stored in the buffer memory 76. The amount of data stored in the buffer memory 76 is monitored by the buffer controller 77 in order to prevent the buffer memory 76 from overflowing. The buffer controller 77 determines the quantization parameter with reference to the amount of data stored in the buffer memory 76 and controls the quantization level in the adaptive quantizing circuit 74 on the basis of the quantization parameter while selecting the transform coefficients to be encoded by the variable-length encoding circuit 75 with reference to the data amount. That is, the buffer controller 77 performs control in such a manner as to increase the data compression rate when the amount of data stored in the buffer memory 76 is large and reduce the compression rate when the amount of stored data is small, thereby preventing the buffer memory 76 from overflowing. The data stored in the buffer memory 76 is read out at a fixed output rate.
With the above configuration, the prior art encoding apparatus attains a reduction in the encoding rate. When a comparison is made between a moving image and a static image, the human eye is more sensitive to a static image than to a moving image. However, the above prior art encoding apparatus does not consider this property of the human eye and performs encoding and weighting processes without varying the encoding conditions or controlling the weighting factors according to whether the image is a moving image or a static image. This gives rise to a problem from the point of view of image compression efficiency.
Furthermore, an image signal is divided into subbands according to the frequency band, and each of the subbands of the image signal is further divided into blocks; however, when an orthogonal transform is performed on each of the resulting subband blocks, since the individual subbands have different frequency characteristics, it is necessary to select a weighting suitable for each subband.